{"id":261,"date":"2017-04-30T14:45:54","date_gmt":"2017-04-30T09:15:54","guid":{"rendered":"http:\/\/www.lokawiz.com\/blog\/?p=261"},"modified":"2017-07-13T19:22:50","modified_gmt":"2017-07-13T13:52:50","slug":"ip-brief-aes-core","status":"publish","type":"post","link":"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/ip-brief-aes-core\/","title":{"rendered":"IP Brief – (Advanced Encryption Standard) AES Core"},"content":{"rendered":"Reading Time: <\/span> < 1<\/span> minute<\/span><\/span>

Overview<\/h3>\n

The (Advanced Encryption Standard) AES Core IP from Lokawiz is a wishbone compliant 128-bit AES engine. It has customization options\u00a0to have multiple configurations, as a wishbone master\u00a0and slave or a pipeline stage from master to slave. In addition, the core is also optimized for area.<\/span><\/p>\n

Features of AES Core<\/h3>\n
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  1. NIST<\/a> compliant, Rijndael encryption and decryption<\/span><\/li>\n
  2. Implements key expansion internally<\/span><\/li>\n
  3. Fully synchronous implementation<\/span><\/li>\n
  4. Very little area requirement for modern FPGAs<\/span><\/li>\n
  5. Wishbone compliant, in multiple configurations<\/span><\/li>\n
  6. 128-bit data block and key length AES implementation<\/span><\/li>\n
  7. Customization for CBC, OFB, and CTR modes available<\/span><\/li>\n<\/ol>\n

    Special Feature<\/h3>\n
      \n
    1. Lesser area requirement than competing cores<\/span><\/li>\n
    2. Supports multiple wishbone configurations<\/span><\/li>\n
    3. FIFO based, allowing for multiple widths of Wishbone bus<\/span><\/li>\n
    4. Customizable FIFO implementations for various FPGA technologies<\/span><\/li>\n<\/ol>\n

      AES Core Deliverable<\/h3>\n

      The Verilog RTL and standalone simulation test-bench. This is\u00a0also deliverable as a custom IP to fit into existing system to get instant security.<\/span><\/p>\n

      Target Applications and Platforms<\/h3>\n
        \n
      1. Applications requiring advanced security for data communication<\/span>\n
          \n
        1. Secure data routing<\/span><\/li>\n
        2. Secure video surveillance systems<\/span><\/li>\n<\/ol>\n<\/li>\n
        3. On-the-fly encryption and decryption of data<\/span><\/li>\n
        4. Crypto processors<\/span><\/li>\n<\/ol>\n

          Why you need this<\/h3>\n

          You are\u00a0interested in adding security to existing FPGA applications in a modular way\u00a0especially if\u00a0you already have a system based on a wishbone bus architecture. Furthermore, this is very useful to you if you also have need for customized secure communications to be added on top of an existing solution.<\/span><\/p>\n

          Visit Us<\/a><\/h3>\n\n\n