{"id":434,"date":"2017-06-25T23:55:19","date_gmt":"2017-06-25T18:25:19","guid":{"rendered":"http:\/\/www.lokawiz.com\/blog\/?p=434"},"modified":"2017-07-13T19:14:46","modified_gmt":"2017-07-13T13:44:46","slug":"rtl-ip-prototype-part-1","status":"publish","type":"post","link":"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-part-1\/","title":{"rendered":"RTL IP Prototype using FPGA Evaluation Kit: Part I"},"content":{"rendered":"<span class=\"span-reading-time rt-reading-time\" style=\"display: block;\"><span class=\"rt-label rt-prefix\">Reading Time: <\/span> <span class=\"rt-time\"> 2<\/span> <span class=\"rt-label rt-postfix\">minutes<\/span><\/span><p style=\"text-align: justify;\">This post, first in the pair of posts, describes Lokawiz RTL IP Prototype setup. We have validated our existing IP cores using this prototype setup.<\/p>\n<h3 style=\"text-align: justify;\">Background<\/h3>\n<p style=\"text-align: justify;\">Lokawiz has very good expertise with\u00a0RTL\u00a0development and verification. We specialize in end-to-end embedded solutions from concept till final production. We have some very high quality RTL IP cores which are ready to plug and play in bigger RTL systems design. These IP cores can also be very easily customized based on system integration requirement of the top level RTL setup. Following is the list of our IP cores along with their description page links.<\/p>\n<ul>\n<li><a href=\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/ip-brief-aes-core\/\" target=\"_blank\" rel=\"noopener noreferrer\">AES Core<\/a><\/li>\n<li><a href=\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/ip-brief-sd-slave-controller\/\" target=\"_blank\" rel=\"noopener noreferrer\">SD Slave Controller<\/a><\/li>\n<li><a href=\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/ip-brief-spi-master-controller\/\" target=\"_blank\" rel=\"noopener noreferrer\">SPI Master Controller<\/a><\/li>\n<\/ul>\n<h3>RTL IP Prototype Description<\/h3>\n<p style=\"text-align: justify;\">We validated the above\u00a0IP Cores with FPGA evaluation Kit from Microsemi and the required peripherals. Our prototype setup\u00a0uses ProASIC3 Starter Kit from Microsemi.\u00a0This kit is also known as A3PE-STARTER-KIT-2. This has a board loaded with a A3PE1500 FPGA. We use Libero software and FlashPro4 programmer for the setup. For more details about the Kit, please visit\u00a0<a href=\"https:\/\/www.microsemi.com\/products\/fpga-soc\/design-resources\/dev-kits\/proasic3\/proasic3-starter-kit\" target=\"_blank\" rel=\"noopener noreferrer\">ProASIC3 Starter Kit<\/a>.<\/p>\n<p style=\"text-align: justify;\"><a href=\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-using-fpga-evaluation-kit-part\/attachment\/rtl-ip-prototype\/\" rel=\"attachment wp-att-627\"><img decoding=\"async\" loading=\"lazy\" class=\"aligncenter size-full wp-image-627\" src=\"http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Prototype.png\" alt=\"RTL IP Prototype\" width=\"1056\" height=\"816\" srcset=\"http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Prototype.png 1056w, http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Prototype-300x232.png 300w, http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Prototype-768x593.png 768w, http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Prototype-1024x791.png 1024w, http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Prototype-950x734.png 950w, http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Prototype-450x348.png 450w\" sizes=\"(max-width: 1056px) 100vw, 1056px\" \/><\/a><\/p>\n<p style=\"text-align: justify;\">The featured image describes the prototype setup. The RTL build with IP cores is programmed into FPGA on the ProASIC3 Starter\u00a0Kit. This Kit\u00a0connects with another board that is an SD Sniffer Board from SparkFun. The Sniffer board\u00a0enables SD card operation and therefore serves\u00a0to connect the board to a computer with an SD card slot. In addition, the Starter Kit\u00a0also connects to\u00a0a\u00a0breakout board mounted with SPI flash memory from Winbond for SPI flash operation.<\/p>\n<h3>RTL IP Prototype Video<\/h3>\n<p style=\"text-align: justify;\">The following video demos the prototype setup.\u00a0 This includes connection between Microsemi Starter Kit, SD Sniffer and SPI flash breakout board along with the pin-out description.<\/p>\n<p style=\"text-align: center;\"><iframe loading=\"lazy\" src=\"https:\/\/www.youtube.com\/embed\/GNuxH63Pz_w\" width=\"720\" height=\"405\" frameborder=\"0\" allowfullscreen=\"allowfullscreen\"><\/iframe><\/p>\n<p style=\"text-align: justify;\">In the next post (<a href=\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-part-2\/\">Part II<\/a>), we will describe the internal connection of IP Cores inside the FPGA. Furthermore, the next\u00a0post will also demo FPGA flashing\u00a0with Libero and a sample running setup.<\/p>\n<h3><a href=\"http:\/\/www.lokawiz.com\/\" target=\"_blank\" rel=\"noopener noreferrer\">Visit Us<\/a><\/h3>\n<tr>\n<td>\n    <script src=\"\/\/platform.linkedin.com\/in.js\" type=\"text\/javascript\"> lang: en_US<\/script><br \/>\n    <script type=\"IN\/FollowCompany\" data-id=\"6441997\"><\/script>\n  <\/td>\n<td>&nbsp;&nbsp;<\/td>\n<td>\n    <a href=\"https:\/\/twitter.com\/Lokawiz\" class=\"twitter-follow-button\" data-show-count=\"false\">Follow @Lokawiz<\/a><br \/>\n    <script async src=\"\/\/platform.twitter.com\/widgets.js\" charset=\"utf-8\"><\/script>\n  <\/td>\n<\/tr>\n","protected":false},"excerpt":{"rendered":"<p><span class=\"span-reading-time rt-reading-time\" style=\"display: block;\"><span class=\"rt-label rt-prefix\">Reading Time: <\/span> <span class=\"rt-time\"> 2<\/span> <span class=\"rt-label rt-postfix\">minutes<\/span><\/span>This post, first in the pair of posts, describes Lokawiz RTL IP Prototype setup. We have validated our existing IP&hellip;<\/p>\n","protected":false},"author":1,"featured_media":627,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"content-type":""},"categories":[11],"tags":[14,17,20,21,13,12,18,19],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v21.5 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>RTL IP Prototype using FPGA Evaluation Kit: Part I - Lokawiz<\/title>\n<meta name=\"description\" content=\"This post, first in the pair of posts, describes Lokawiz RTL IP Prototype setup. We have validated our existing IP cores using this prototype setup.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-part-1\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"RTL IP Prototype using FPGA Evaluation Kit: Part I - Lokawiz\" \/>\n<meta property=\"og:description\" content=\"This post, first in the pair of posts, describes Lokawiz RTL IP Prototype setup. We have validated our existing IP cores using this prototype setup.\" \/>\n<meta property=\"og:url\" content=\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-part-1\/\" \/>\n<meta property=\"og:site_name\" content=\"Lokawiz\" \/>\n<meta property=\"article:publisher\" content=\"http:\/\/www.facebook.com\/lokawiz\" \/>\n<meta property=\"article:author\" content=\"www.facebook.com\/lokawiz\" \/>\n<meta property=\"article:published_time\" content=\"2017-06-25T18:25:19+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2017-07-13T13:44:46+00:00\" \/>\n<meta property=\"og:image\" content=\"http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Prototype.png\" \/>\n\t<meta property=\"og:image:width\" content=\"1056\" \/>\n\t<meta property=\"og:image:height\" content=\"816\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/png\" \/>\n<meta name=\"author\" content=\"Lokawiz\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@Lokawiz\" \/>\n<meta name=\"twitter:site\" content=\"@Lokawiz\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"Lokawiz\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"2 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-part-1\/#article\",\"isPartOf\":{\"@id\":\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-part-1\/\"},\"author\":{\"name\":\"Lokawiz\",\"@id\":\"http:\/\/www.lokawiz.com\/blog\/#\/schema\/person\/f6123129b2bbfb1e2a39f6e1e8363334\"},\"headline\":\"RTL IP Prototype using FPGA Evaluation Kit: Part I\",\"datePublished\":\"2017-06-25T18:25:19+00:00\",\"dateModified\":\"2017-07-13T13:44:46+00:00\",\"mainEntityOfPage\":{\"@id\":\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-part-1\/\"},\"wordCount\":337,\"commentCount\":0,\"publisher\":{\"@id\":\"http:\/\/www.lokawiz.com\/blog\/#organization\"},\"keywords\":[\"AES Core\",\"FPGA\",\"Microsemi\",\"ProASIC3\",\"Prototype\",\"RTL IP\",\"SD Slave Controller\",\"SPI Master Controller\"],\"articleSection\":[\"Hardware IP\"],\"inLanguage\":\"en\",\"potentialAction\":[{\"@type\":\"CommentAction\",\"name\":\"Comment\",\"target\":[\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-part-1\/#respond\"]}]},{\"@type\":\"WebPage\",\"@id\":\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-part-1\/\",\"url\":\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-part-1\/\",\"name\":\"RTL IP Prototype using FPGA Evaluation Kit: Part I - Lokawiz\",\"isPartOf\":{\"@id\":\"http:\/\/www.lokawiz.com\/blog\/#website\"},\"datePublished\":\"2017-06-25T18:25:19+00:00\",\"dateModified\":\"2017-07-13T13:44:46+00:00\",\"description\":\"This post, first in the pair of posts, describes Lokawiz RTL IP Prototype setup. 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