{"id":555,"date":"2017-07-04T16:39:57","date_gmt":"2017-07-04T11:09:57","guid":{"rendered":"http:\/\/www.lokawiz.com\/blog\/?p=555"},"modified":"2017-07-13T19:29:51","modified_gmt":"2017-07-13T13:59:51","slug":"rtl-ip-prototype-part-2","status":"publish","type":"post","link":"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-part-2\/","title":{"rendered":"RTL IP Prototype using FPGA Evaluation Kit: Part II"},"content":{"rendered":"<span class=\"span-reading-time rt-reading-time\" style=\"display: block;\"><span class=\"rt-label rt-prefix\">Reading Time: <\/span> <span class=\"rt-time\"> 2<\/span> <span class=\"rt-label rt-postfix\">minutes<\/span><\/span><p style=\"text-align: justify;\">This post, final in the pair of posts, describes Lokawiz RTL IP Prototype setup. The first post in this series is available at <a href=\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-using-fpga-evaluation-kit-part\/\">Part I<\/a>.\u00a0This\u00a0post (Part II) finally describes the internal connection of IP Cores inside the FPGA in\u00a0<a href=\"https:\/\/www.microsemi.com\/products\/fpga-soc\/design-resources\/dev-kits\/proasic3\/proasic3-starter-kit\" target=\"_blank\" rel=\"noopener noreferrer\">ProASIC3 Starter Kit<\/a> from Microsemi. Furthermore, it also demos FPGA flashing\u00a0with Libero and a sample running setup.<\/p>\n<h3 style=\"text-align: justify;\">Background<\/h3>\n<p style=\"text-align: justify;\">Lokawiz has very good expertise with\u00a0RTL\u00a0development and verification. We specialize in end-to-end embedded solutions from concept till final production. We have some very high quality RTL IP cores which are ready to plug and play in bigger RTL systems design. These IP cores can also be very easily customized based on system integration requirement of the top level RTL setup. Following is the list of our IP cores along with their description page links.<\/p>\n<ul>\n<li><a href=\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/ip-brief-aes-core\/\" target=\"_blank\" rel=\"noopener noreferrer\">AES Core<\/a><\/li>\n<li><a href=\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/ip-brief-sd-slave-controller\/\" target=\"_blank\" rel=\"noopener noreferrer\">SD Slave Controller<\/a><\/li>\n<li><a href=\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/ip-brief-spi-master-controller\/\" target=\"_blank\" rel=\"noopener noreferrer\">SPI Master Controller<\/a><\/li>\n<\/ul>\n<h3>RTL IP Connections<\/h3>\n<p style=\"text-align: justify;\">The featured image describes the RTL IP connections inside the FPGA in ProASIC3 Starter Kit from Microsemi. An SPI Sniffer board from SparkFun connects to the Starter Kit to enable SD operations. In addition, a\u00a0breakout board mounted with Winbond SPI flash also connects to the Starter Kit for memory operation.<\/p>\n<p style=\"text-align: justify;\"><a href=\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-part-2\/attachment\/rtl-ip-integration\/\" rel=\"attachment wp-att-631\"><img decoding=\"async\" loading=\"lazy\" class=\"aligncenter size-full wp-image-631\" src=\"http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Integration.png\" alt=\"RTL IP Integration\" width=\"1056\" height=\"816\" srcset=\"http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Integration.png 1056w, http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Integration-300x232.png 300w, http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Integration-768x593.png 768w, http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Integration-1024x791.png 1024w, http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Integration-950x734.png 950w, http:\/\/www.lokawiz.com\/blog\/wp-content\/uploads\/2017\/06\/RTL-IP-Integration-450x348.png 450w\" sizes=\"(max-width: 1056px) 100vw, 1056px\" \/><\/a><\/p>\n<p style=\"text-align: justify;\">The FPGA Controller controls the flow of data between SD card and the SPI flash memory. Furthermore, it uses the\u00a0AES Engine to encrypt and decrypt the data. The SPI Flash memory contains the encrypted data whereas SD Card contains normal data readable by a computer machine. For the Starter Kit, the data flow works at 2MB\/s at\u00a0SD side interface and at less than 6MB\/s at\u00a0SPI side interface.<\/p>\n<p style=\"text-align: justify;\">The data flows in both the directions are described below:<\/p>\n<h4>SD Card to SPI Flash<\/h4>\n<p style=\"text-align: justify;\">First of all, the SD Slave Interface reads data from SD Card through SD Sniffer Board. \u00a0Then the FPGA Controller uses AES Engine to encrypt this data. Finally, SPI Flash Interface writes the encrypted data into SPI Flash memory.<\/p>\n<h4>SPI Flash to SD Card<\/h4>\n<p style=\"text-align: justify;\">The data flow in this direction goes as follows. First of all, SPI Flash Interface reads the encrypted data from SPI Flash memory. Then, FPGA controller uses AES Engine to decrypt the encrypted data. Finally, SD Slave Interface writes the data into SD Card the the Sniffer Board.<\/p>\n<h3>Programming FPGA with RTL IP build<\/h3>\n<p style=\"text-align: justify;\">The following video demos how to burn the FPGA with the build containing\u00a0RTL IPs. We used FlashPro4 and Libero software to flash the FPGA on the ProASIC3 Kit.<\/p>\n<p style=\"text-align: center;\"><iframe loading=\"lazy\" src=\"https:\/\/www.youtube.com\/embed\/R-ldmA7JYtE\" width=\"720\" height=\"405\" frameborder=\"0\" allowfullscreen=\"allowfullscreen\"><\/iframe><\/p>\n<h3>Prototype Setup Run<\/h3>\n<p style=\"text-align: justify;\">The following video demos a sample run for the prototype and evaluation setup. In this video please\u00a0observe that the SD Sniffer board is\u00a0soldered to ProASIC3 board. This was necessary to avoid the signal integrity issue which we faced with\u00a0board connection using connecting wires as shown in <a href=\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-using-fpga-evaluation-kit-part\/\" target=\"_blank\" rel=\"noopener noreferrer\">Part I<\/a>\u00a0setup demo video.<\/p>\n<p style=\"text-align: center;\"><iframe loading=\"lazy\" src=\"https:\/\/www.youtube.com\/embed\/v4P6ABgI2tI\" width=\"720\" height=\"405\" frameborder=\"0\" allowfullscreen=\"allowfullscreen\"><\/iframe><\/p>\n<h3><a href=\"http:\/\/www.lokawiz.com\/\" target=\"_blank\" rel=\"noopener noreferrer\">Visit Us<\/a><\/h3>\n<tr>\n<td>\n    <script src=\"\/\/platform.linkedin.com\/in.js\" type=\"text\/javascript\"> lang: en_US<\/script><br \/>\n    <script type=\"IN\/FollowCompany\" data-id=\"6441997\"><\/script>\n  <\/td>\n<td>&nbsp;&nbsp;<\/td>\n<td>\n    <a href=\"https:\/\/twitter.com\/Lokawiz\" class=\"twitter-follow-button\" data-show-count=\"false\">Follow @Lokawiz<\/a><br \/>\n    <script async src=\"\/\/platform.twitter.com\/widgets.js\" charset=\"utf-8\"><\/script>\n  <\/td>\n<\/tr>\n","protected":false},"excerpt":{"rendered":"<p><span class=\"span-reading-time rt-reading-time\" style=\"display: block;\"><span class=\"rt-label rt-prefix\">Reading Time: <\/span> <span class=\"rt-time\"> 2<\/span> <span class=\"rt-label rt-postfix\">minutes<\/span><\/span>This post, final in the pair of posts, describes Lokawiz RTL IP Prototype setup. The first post in this series&hellip;<\/p>\n","protected":false},"author":1,"featured_media":631,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"content-type":""},"categories":[11],"tags":[14,69,17,70,20,21,13,12,18,19],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v21.5 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>RTL IP Prototype using FPGA Evaluation Kit: Part II - Lokawiz<\/title>\n<meta name=\"description\" content=\"RTL IP Prototype Part II describes the internal connection of IP cores inside the FPGA in ProASIC3, demos FPGA flashing and a sample running setup.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"http:\/\/www.lokawiz.com\/blog\/product\/hw-ip\/rtl-ip-prototype-part-2\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"RTL IP Prototype using FPGA Evaluation Kit: Part II - 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