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AES Core

IP Brief – (Advanced Encryption Standard) AES Core

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Overview

The (Advanced Encryption Standard) AES Core IP from Lokawiz is a wishbone compliant 128-bit AES engine. It has customization options to have multiple configurations, as a wishbone master and slave or a pipeline stage from master to slave. In addition, the core is also optimized for area.

Features of AES Core

  1. NIST compliant, Rijndael encryption and decryption
  2. Implements key expansion internally
  3. Fully synchronous implementation
  4. Very little area requirement for modern FPGAs
  5. Wishbone compliant, in multiple configurations
  6. 128-bit data block and key length AES implementation
  7. Customization for CBC, OFB, and CTR modes available

Special Feature

  1. Lesser area requirement than competing cores
  2. Supports multiple wishbone configurations
  3. FIFO based, allowing for multiple widths of Wishbone bus
  4. Customizable FIFO implementations for various FPGA technologies

AES Core Deliverable

The Verilog RTL and standalone simulation test-bench. This is also deliverable as a custom IP to fit into existing system to get instant security.

Target Applications and Platforms

  1. Applications requiring advanced security for data communication
    1. Secure data routing
    2. Secure video surveillance systems
  2. On-the-fly encryption and decryption of data
  3. Crypto processors

Why you need this

You are interested in adding security to existing FPGA applications in a modular way especially if you already have a system based on a wishbone bus architecture. Furthermore, this is very useful to you if you also have need for customized secure communications to be added on top of an existing solution.

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