Category: Hardware IP
RTL Hardware IP information.
RTL IP Prototype using FPGA Evaluation Kit: Part II
This post, final in the pair of posts, describes Lokawiz RTL IP Prototype setup. The first post in this series is available at Part I. This post (Part II) finally describes the internal connection of IP Cores inside the …
RTL IP Prototype using FPGA Evaluation Kit: Part I
This post, first in the pair of posts, describes Lokawiz RTL IP Prototype setup. We have validated our existing IP cores using this prototype setup.
Background
Lokawiz has very good expertise with RTL development and verification. We specialize in end-to-end …
IP Brief – (Serial Peripheral Interface) SPI Master Controller
Overview
The SPI (Serial Peripheral Interface) bus is an industry standard peripheral bus used extensively for interfacing with memory, ADCs, DACs, sensors, e.t.c. Our SPI Master Controller IP provides an easy path to incorporate such devices in a system without …
IP Brief – (Secured Digital) SD Slave Controller
Overview
SD Slave (Secure Digital Slave) controller IP is designed for memory access. It captures data from SD bus and makes it available onto the wishbone interface. It also reads data from wishbone to transmit over SD bus. The core …
IP Brief – (Advanced Encryption Standard) AES Core
Overview
The (Advanced Encryption Standard) AES Core IP from Lokawiz is a wishbone compliant 128-bit AES engine. It has customization options to have multiple configurations, as a wishbone master and slave or a pipeline stage from master to slave. In …