Overview
The SPI (Serial Peripheral Interface) bus is an industry standard peripheral bus used extensively for interfacing with memory, ADCs, DACs, sensors, e.t.c. Our SPI Master Controller IP provides an easy path to incorporate such devices in a system without a dedicated processor for SPI interfacing.
Features of SPI Master Controller
- Standard 4-pin implementation of SPI interface
- Higher level support for interfacing with Flash memories
- Supports all SPI mode combinations of CPOL and CPHA
- Wishbone interface for simple interfacing with rest of system
- Supports single bit duplex communication
Special Features
- Customizable to implement different higher level protocols over SPI interface
- Modifiable to support interrupt generation when long duration action on peripheral side is complete
- Validated with Spansion and Winbond SPI Flash memories
SPI Master Controller Deliverable
Verilog RTL and standalone test-bench. Also deliverable as a custom IP with higher level protocol implemented over SPI interface.
Target Applications and Platforms
- Solutions looking for quick interfacing with SPI Flash memories
- Systems that have wishbone interface and wish to offload SPI level details
- Data logging systems and IoT solutions that interface with SPI sensors
Why you need this
If you are building solutions that use sensors or memory with an SPI interface, our SPI Master Controller IP is especially relevant for you. Furthermore, it can make your solutions more robust to manufacturer changes in the protocol built on top of SPI. So, for instance if two manufacturers have ADCs with SPI, but slightly different mechanisms of interfacing with the ADC, we can customize our SPI Master Controller IP to support both manufacturers allowing for multiple sourcing of sensor parts.
