This post, first in the pair of posts, describes Lokawiz RTL IP Prototype setup. We have validated our existing IP cores using this prototype setup.
Lokawiz has very good expertise with RTL development and verification. We specialize in end-to-end embedded solutions from concept till final production. We have some very high quality RTL IP cores which are ready to plug and play in bigger RTL systems design. These IP cores can also be very easily customized based on system integration requirement of the top level RTL setup. Following is the list of our IP cores along with their description page links.
RTL IP Prototype Description
We validated the above IP Cores with FPGA evaluation Kit from Microsemi and the required peripherals. Our prototype setup uses ProASIC3 Starter Kit from Microsemi. This kit is also known as A3PE-STARTER-KIT-2. This has a board loaded with a A3PE1500 FPGA. We use Libero software and FlashPro4 programmer for the setup. For more details about the Kit, please visit ProASIC3 Starter Kit.
The featured image describes the prototype setup. The RTL build with IP cores is programmed into FPGA on the ProASIC3 Starter Kit. This Kit connects with another board that is an SD Sniffer Board from SparkFun. The Sniffer board enables SD card operation and therefore serves to connect the board to a computer with an SD card slot. In addition, the Starter Kit also connects to a breakout board mounted with SPI flash memory from Winbond for SPI flash operation.
RTL IP Prototype Video
The following video demos the prototype setup. This includes connection between Microsemi Starter Kit, SD Sniffer and SPI flash breakout board along with the pin-out description.
In the next post (Part II), we will describe the internal connection of IP Cores inside the FPGA. Furthermore, the next post will also demo FPGA flashing with Libero and a sample running setup.